This application claims benefit of priority from provisional patent application 60/022,121, filed Jul. 17, 1996 and incorporated herein by reference.
The present invention relates to the field of data processing. In particular, it relates to the use of data compression in programming programmable logic devices.
Coassigned U.S. Pat. No. 5,563,592, entitled, PROGRAMMABLE LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION FILE AND ASSOCIATED DECOMPRESSION and incorporated herein by reference to the extent necessary to understand the invention, discusses the desirability of using run-length encoding and decoding schemes for compressing the amount of configuration data that must be stored in order to program a programmable logic device. Run-length encoding has many applications. In programmable logic devices, however, one application for run length encoding allows the encoding to be done in a computationally intensive way in software, while the decoding is performed in a simple way on circuitry connected to the programmable logic device.
As the complexity of the programmable logic devices grows, so does the number of programmable elements used requiring configuration files with a greater number of "1s" and "0s" to program the programmable memory devices. As the size of the configuration files increases, so does the size of the EPROMs needed to store them. Large EPROMs are expensive and require large silicon area to be manufactured. The size of the silicon area is more important when the EPROM is manufactured on the same substrate as the programmable logic device. The size of the EPROMs limit the complexity of the programmable logic device.
What is needed is an apparatus and method for further reducing the size of the configuration files used in a programmable logic device before they are stored in memory. Such techniques have applications in other areas where run-length encoding is desirable.